1. Field of the Invention
The present invention relates to a circuit for driving an array of elements such as light-emitting diodes used as light sources in an electrophotographic printer or resistive heat-emitting elements used as heat sources in a thermal printer, and to an array head incorporating this circuit.
2. Description of the Related Art
As an example of a conventional circuit for driving an array of elements, Japanese Unexamined Patent Application Publication No. 9-174918 discloses a circuit for driving an array of light-emitting diodes (hereinafter, LEDs) in an electrophotographic printer. This circuit and printer will be described below with reference to FIGS. 16 to 24.
In the printer, the LED array selectively illuminates a charged photosensitive drum to form a latent image, which is developed by application of toner to form a toner image, and the toner image is transferred to and fused onto a sheet of paper. The control system of the printer is shown in FIG. 16. The printing control unit 1 is a computing device comprising a microprocessor, read-only memory (ROM), random-access memory (RAM), input-output ports, timers, and other facilities. Upon receiving signals SG1, SG2, etc. from a higher-order controller (not visible), the printing control unit 1 generates signals that control a sequence of operations for printing dot-mapped data. The data are provided in signal SG2, which is sometimes referred to as a video signal because it supplies the dot-mapped data one-dimensionally.
The printing sequence starts when the printing control unit 1 receives a printing command from the higher-order controller by means of control signal SG1. First, a temperature (Temp.) sensor 23 is checked to determine whether a fuser 22 is at the necessary temperature for printing. If it is not, current is fed to a heater 22a to raise the temperature of the fuser 22.
When the fuser 22 is ready, the printing control unit 1 commands a motor driver 2 to drive a develop-transfer process motor (PM) 3, activates a charge signal SGC to turn on a high-voltage (HV) charging power source 25, and thereby charges the developing unit (D) 27.
In addition, a paper sensor 8 is checked to confirm that paper is present in a cassette (not visible), and a size sensor 9 is checked to determine the size of the paper. If paper is present, another motor driver 4 drives a paper transport motor (PM) 5 according to the size of the paper, first in one direction to transport the paper to a starting position sensed by a pick-up sensor 6, then in the opposite direction to transport the paper into the printing mechanism.
When the paper is in position for printing, the printing control unit 1 sends the higher-order controller a timing signal SG3 (including a main scanning synchronization signal and a sub-scanning synchronization signal) as shown in FIG. 17. The higher-order controller responds by sending the dot data for one page in the video signal SG2. The printing control unit 1 sends corresponding dot data (HD-DATA) to an LED head 19 in synchronization with a clock signal (HD-CLK). The LED head 19 comprises a linear array of LEDs for printing respective dots (also referred to as picture elements or pixels).
After receiving data for one line of dots in the video signal SG2 and sending the data to the LED head 19, the printing control unit 1 sends the LED head 19 a latch signal (HD-LOAD), causing the LED head 19 to store the print data (HD-DATA). The print data stored in the LED head 19 can then be printed while the printing control unit 1 is receiving the next print data from the higher-order controller in the video signal SG2.
The video signal SG2 is transmitted and received one printing line at a time. FIG. 17 illustrates the printing of three consecutive dot lines Nxe2x88x921, N, and N+1. For each line, the LED head 19 forms a latent image of dots with a comparatively high electric potential on the negatively charged photosensitive drum (not visible). In the developing unit 27, negatively charged toner is electrically attracted to the dots, forming a toner image.
The toner image is then transported to a transfer unit (T) 28. The printing control unit 1 activates a high-voltage transfer power source 26 by sending it a transfer signal SG4, and the toner image is transferred to a sheet of paper passing between the photosensitive drum and transfer unit 28. The sheet of paper carrying the transferred toner image is transported to the fuser 22, where the toner image is fused onto the paper by heat generated by the heater 22a. Finally, the sheet of paper carrying the fused toner image is transported out of the printing mechanism, passing an exit sensor 7, and ejected from the printer.
The printing control unit 1 controls the high-voltage transfer power source 26 according to the information detected by the pick-up sensor 6 and size sensor 9 so that voltage is applied to the transfer unit 28 only while paper is passing through the transfer unit 28. When the paper passes the exit sensor 7, the printing control unit 1 stops the supply of voltage from the high-voltage charging power source 25 to the developing unit 27, and halts the develop/transfer process motor 3. The above operations are repeated to print a series of pages.
FIG. 18 is a simplified schematic drawing showing the circuit structure of the LED head 19. The print data signal HD-DATA and clock signal HD-CLK are used to shift bit data for two thousand four hundred ninety-six dots, a number suitable for printing on A4-size paper at a resolution of three hundred dots per inch, into a shift register comprising flip-flops FF1, FF2, . . . , FF2496. The latch signal HD-LOAD causes latches LT1, LT2, . . . , LT2496 to latch the bit data. The strobe signal HD-STB-N activates a circuit comprising an inverter G0, pre-buffers G1, G2, . . . , G2496, and switching elements Tr1, Tr2, . . . , Tr2496 that drive a linear array of light-emitting elements LD1, LD2, . . . , LD2496 according to the latched bit data. The switching elements are p-channel metal-oxide-semiconductor (MOS) transistors; the light-emitting elements are LEDs.
The LED head 19 is supplied with power at a voltage denoted VDD in this drawing and the next. Some of this power is supplied as current to drive the LEDs. The notation VDDH will be used later to denote the voltage of the LED driving power supply.
As shown in FIG. 19, the LED head 19 comprises a plurality of LED array chips 101 driven by corresponding driver integrated circuits (ICs) 100. In this example, there are twenty-six LED array chips and twenty-six driver ICs. The driver ICs 100 are connected in cascade. Each LED array chip 101 includes ninety-six LEDs. The LED head 19 also has a reference voltage generator 102 for supplying a reference voltage Vref to the driver ICs 100.
Each driver IC 100 has the same internal circuit configuration, comprising: a shift register 100a with ninety-six flip-flops that receive the printing data (HD-DATA) in synchronization with the clock signal (HD-CLK); a latch circuit 100b that latches the output signals from the shift register 100a in response to the latch signal (HD-LOAD); an inverter 100e that inverts the strobe signal (HD-STB-N) from negative to positive logic; an AND logic circuit 100c that gates the output signals from the latch circuit 100b according to the output of the inverter 100e; an LED driving circuit 100d that supplies driving current to the LEDs in the corresponding LED array chip 101 in response to the output signals of the AND circuit 100c; and a control voltage generator 100f that supplies a control voltage to the LED driving circuit 100d. 
In the printing process, when the HD-DATA, HD-CLK, HD-LOAD, and HD-STB-N signals are sent from the printing control unit 1 to the LED head 19, the LEDs that are driven are driven simultaneously for the same length of time, as determined by the strobe signal HD-STB-N (this time is denoted LDT in FIG. 17). Any variations in the electrical characteristics of transistors Tr1, Tr2, . . . , Tr2496 and LEDs LD1, LD2, . . . , LD2496 may therefore lead to variations in the driving current, thus to variations in the intensity of the emitted light. As a result, the dots in the latent image formed on the photosensitive drum may differ in size, leading to printed dots of different sizes.
FIG. 20 shows an example of the above variations in LED driving current and dot size. DRV1 to DRV26 are driver ICs that drive LED array chips CHP1 to CHP26, respectively. The ninety-six LEDs in each LED array chip are wire-bonded to corresponding output terminals of the driver ICs, as will be shown in FIG. 23. The twenty-six driver ICs in FIG. 20 are connected so that externally input printing data are transferred serially from one driver IC to the next.
Although it is desirable for each of the driver ICs DRV1 to DRV26 to supply the same amount of driving current to the LEDs it drives, circuit-element characteristics vary according to various factors in the semiconductor fabrication processes, so there is inevitably some variation in the driving current. As noted above, this variation leads to variations in the amount of light (the optical power) emitted by each LED, so that the photosensitive drum receives uneven exposure energy, and different-sized dots are developed. On a printed page consisting mainly of text, the dot-size variations are rarely noticed, but when a natural image such as a photograph is printed, the dot-size variations become perceptible as variations in printing density, causing undesirable printing quality defects.
To avoid such printing defects, the LED array head manufacturer screens the driver ICs, selects those in which the driving-current variation does not exceed a certain limit xcex94I, groups these driver ICs according to their average driving current, and assembles each LED head with driver ICs taken from the same group.
Further details of the driver ICs will now be described. FIG. 21 shows the connection relationships between the pre-buffers G1, G2, . . . , G2496 in FIG. 18 and their peripheral circuits, showing the circuit elements (LT1, G1, Tr1, LD1) related to the first dot. Pre-buffer G1 includes an AND gate AD1, a p-channel MOS transistor TP1, and an n-channel MOS transistor TN1.
FIG. 21 also shows the control voltage generator 100f, which includes an operational amplifier 200, a reference resistance Rref, and a p-channel MOS transistor 201 that functions as a reference transistor. The reference transistor 201 and the p-channel MOS transistors Tr1, Tr2, . . . , Tr2496 that function as switching elements in FIG. 18 have the same gate length, and receive the same voltage VDDH at their source electrodes. For simplicity, it will be assumed below that the reference transistor 201 also has the same gate width as transistors Tr1, Tr2, . . . , Tr2496.
The operational amplifier 200 receives the reference voltage Vref supplied from the reference voltage generator 102 in FIG. 19 at its inverting input terminal, and outputs a control voltage Vcontrol to the gate electrode of the reference transistor 201. The operational amplifier 200, reference transistor 201, and reference resistance Rref are interconnected to form a feedback control circuit that holds the current Iref flowing through the reference transistor 201 and reference resistance Rref to a constant value determined by Vref and Rref. In effect, the control voltage generator 100f detects VDDH and generates a control voltage Vcontrol that produces a constant reference current Iref despite variations in VDDH.
Vcontrol is also supplied through pre-buffer G1 to the gate electrode of transistor Tr1 to switch transistor Tr1 on. When switched on, transistor Tr1 supplies LED LD1 with a constant current equal to the reference current Iref and independent of VDDH.
FIG. 22 schematically shows the layout of a conventional driver IC 300, such as the driver IC disclosed in Japanese Unexamined Patent Application Publication No. 6-297765. This driver IC 300 is a rectangular chip with a row of electrodes 301 arranged along one longitudinal edge for input and output of signals such as HD-DATA, HD-CLK, HD-LOAD, and HD-STB-N. Disposed above this row of electrodes 301, in order from bottom to top in the drawing, are a shift register 302, a latch circuit 303, a pre-buffer circuit 304 including AND gates and inverters, a conductive member 305 used as a ground pattern for the pre-buffer circuit 304, an LED driving power supply electrode or VDDH electrode 306, a row of LED driving transistors 307, and a staggered double row of LED driving electrodes 308. The ninety-six LED driving electrodes DO1, DO2, . . . , DO95, DO96 in the double row are aligned with the associated driving transistors 307 and with other associated circuit elements in circuits 302-304, as indicated by the vertical lines in the drawing. The input and output signal electrodes 301 and LED driving electrodes 308 are aluminum pads.
The VDDH electrode 306 is an aluminum band of width W, disposed between and parallel to the row of pre-buffers 304 and the row of LED driving transistors 307. A plurality of electrode pads 309 are formed on the VDDH electrode 306 to receive power at voltage VDDH from an external source (not shown). In the drawing, there are three electrode pads 309, aligned with LED driving electrodes DO16, DO48, and DO80.
FIG. 23 shows a schematic side view of the driver IC 300 in FIG. 22. The input and output signal electrodes 301 and VDDH electrode pads 309 are connected by bonding wires 310 to corresponding electrodes on a printed wiring board (not visible) on which the driver IC is mounted. The LED driving electrodes 308 are connected by bonding wires 311 to corresponding electrodes on an LED array chip (not visible).
FIG. 24 is an equivalent circuit diagram showing the ninety-six p-channel MOS driving transistors M1, M2, . . . , M96 that function as switching elements in one driver IC, and the driven LEDs D1, D2, . . . , D96. These transistors and LEDs correspond to the transistors and LEDs denoted Tr1, Tr2, . . . and LD1, LD2, . . . in FIGS. 18 and 21. Also shown is a reference transistor M0 equivalent to the reference transistor 201 in FIG. 21. The position of reference transistor M0 is indicated by hatching in FIG. 22.
The source electrodes of transistors M1, M2, . . . , M96 are connected to the VDDH electrode 306 at nodes S1, S2, . . . , S96 in FIG. 24. The resistance of the VDDH electrode 306 between these nodes is modeled by resistors R1, R2, . . . , R95. An additional resistor R0 models the resistance between node S1 and the source electrode of reference transistor M0. The resistance of the three bonding wires 310 that supply power to the VDDH electrode 306 is modeled by resistors R201, R202, R203. Given the layout shown in FIG. 22, in which the VDDH electrode pads 309 are aligned with LED driving electrodes DO16, DO48, DO80, these resistors R201, R202, R203 can be considered to be connected to the source electrodes of driving transistors M16, M48, M80 at nodes S16, S48, S80, respectively.
The drain electrodes of driving transistors M1, M2, . . . , M96 are connected to the anode electrodes of LEDs D1, D2, . . . , D96. When switched on, the driving transistors M1, M2, . . . , M96 supply current Io to the corresponding LEDs at a rate determined by their gate-source voltage, which depends on the control voltage Vcontrol generated by the control voltage generator shown in FIG. 21.
In FIGS. 22 and 24, driving transistor M1 and reference transistor M0 are mutually adjacent and therefore have substantially identical electrical characteristics and gate-source voltages. The current Io supplied by driving transistor M1 is therefore substantially equal to the constant reference current Iref flowing through reference transistor M0, as desired. In the driver IC as a whole, however, the driving current may vary, making it necessary to screen out driver ICs in which the variation exceeds a limit xcex94I, as noted above.
Referring again to FIG. 20, there tends to be little difference in the driving current supplied by the driving transistors at mutually adjacent dot positions within one driver IC chip. Furthermore, the variation within the driver IC chip as a whole tends to be a monotonic increase or decrease according to the dot position, for the following reason.
The driver ICs are formed on a circular silicon wafer on which electrical characteristics such as MOS transistor threshold voltages usually show a concentric pattern of variation. A driver IC chip formed near the periphery of the wafer, at a point where the long axis of the chip aligns with the concentric pattern, will display little variation in driving current, but only a few such chips can be obtained from each wafer. Most of the chips are disposed in positions where their long axes cut across the concentric pattern, producing driving current that increases or decreases from one dot to the next along the length of the chip.
As shown in FIG. 20, even if two adjacent driver ICs have the same average driving current value, if they both have the same increasing or decreasing pattern of dot-to-dot current variation, there may be a considerable difference in driving current between the dot at one end of one chip and the adjacent dot at the adjacent end of the other chip. Moreover, even if the dot-to-dot variation within each driver IC chip is xcex94I or less, the variation within the whole head may be as large as 2xcex94I in the worst case.
Thus despite the screening of the driver chips, there can be a significant difference in driving current between two mutually adjacent dot positions on different chips, leading to an abrupt change in printing density that persists in the vertical direction on the printed page. While gradual variations in printing density often go unnoticed, the human eye readily perceives an abrupt, persistent change.
An object of the present invention is accordingly to reduce the size of abrupt element-to-element variations in driving current supplied to an array of driven elements.
Another object of the invention is to reduce gradual variations in the driving current.
The invention provides a driving circuit that drives an array of driven elements. The driving circuit includes an array of driving elements that receive a control voltage, and selectively supply current from a power supply to the driven elements at a rate responsive to the difference between the control voltage and the power supply voltage. The control voltage is furnished to the driving elements through a conductive member that extends parallel to the array of driving elements. The driving circuit includes means for adjusting the control voltage independently at each end of the conductive member.
According to one aspect of the invention, the means for adjusting comprises a pair of control voltage generators. One control voltage generator includes a reference element disposed at a first end of the array of driving elements, and supplies a first control voltage, responsive to the power supply voltage at the first end of the array, to the first end of the conductive member. The other control voltage generator includes a reference element disposed at a second end of the array of driving elements, and supplies a second control voltage, responsive to the power supply voltage at the second end of the array, to the second end of the conductive member.
In this aspect of the invention, the control voltage supplied to a driven element varies between the first and second control voltages according to the position of the driven element between the two ends of the array, thereby counteracting variations in electrical characteristics in the array and reducing variations in driving current. In particular, the driving current supplied by the driving elements at the two ends of the array can be controlled to substantially the same value, so that in an array head employing a plurality of these driving circuits, there are no abrupt changes in driving current from one driving circuit to the next.
According to another aspect of the invention, the control voltage is supplied to the center of the conductive member by a single control voltage generator, and the means for adjusting includes a pair of control voltage adjustment circuits, disposed at mutually opposite ends of the conductive member, that can be independently set to source or sink current, thereby independently raising or lowering the control voltage at the two ends of the conductive member. These control voltage adjustments can reduce gradual variations in driving current across the array.
The single control voltage generator may include a single reference element disposed in the middle of the array of driving elements, or two reference elements disposed at mutually opposite ends of the array. The control voltage supplied to the center of the conductive member may thus be responsive to the power supply voltage at the middle of the array, or to the average of the power supply voltages at the two ends of the array.
The driving elements and reference elements are, for example, transistors with gate electrodes receiving the control voltage.